It is well known in the art to form split-gate memory cells as an array of such cells. For example, U.S. Pat. No. 7,868,375 (incorporated herein by reference for all purposes) discloses an array of memory cells, where each memory cell includes a floating gate, a control or coupling gate, a select gate, an erase gate, all formed on a substrate with a channel region defined between a source and drain regions. For efficient use of space, the memory cells are formed in pairs, with each pair sharing a common source region and erase gate.
It is also known to form both low voltage and high voltage logic devices on the same wafer die as the array of memory cells. Such logic devices can include transistors each having a source and drain, and a poly gate controlling the conductivity of the channel region between the source and drain.